Block designing using IP Integrator for AP SoC (Zynq)

In this blog I will guide you how to create a design for Zynq platform using Vivado IP Integrator.

1.  Launch Vivado

2. Select Create Project


3. Select Next

4. Type project name and enter project location

 5. Select Next

6. Check RTL project

7. Select Next and skip the next two steps

8. Select your target board


9. Select Next

10. Select Finish

11. Select Create Block Design under IP Integrator in the left pane of Vivado


12. Enter design name

13. Select OK

14. Add Zynq Processing System IP to your block design by clicking Add IP icon in block design pane

15. Type Zynq and add IP


16. Select Run Block Automation

17. Check All Automation

18. Select OK


19. Repeat Step 14 and add GPIO IP

20. Double click GPIO IP

21. Select leds 4bits in Board Interface

22. Select OK



23. Select Run Connection Automation

24. Check All Automation

25. Select OK

26. Final block design should look like as shown below


27. Right click on block design and select Create HDL Wrapper



28. Select OK

29. Run Synthesis

30. Run Implementation

31. Generate Bitstream.



Congratulation you have successfully completed your first project for Zynq platform